Hardware Implementation Analysis for Digital Filters

An elaborate analysis for various hardware implementations of digital filters is presented in this paper. A bit-true model of a sample digital filter is extracted from simulation based on the effects of finite word-length arithmetic. According to the extracted implementation parameters, four different hardware implementation methods are explored and compared. The bit-true model is described in Verilog HDL for the four different methods: fully combinational, word-serial, bit-serial and combinational-sequential. The implemented modules are tested with a self-checking test-bench that reads the extracted test cases from MATLAB bit-true model, applies them to the hardware model, and checks the output for equivalence. Also, the developed models are synthesized for 0.35 μm CMOS ASIC library and VirtexII Pro FPGA devices. According to the synthesis results, wordserial and fully-combinational methods bear less implementation area and delay complexities, respectively. The other methods compromise between hardware implementation constraints such as area and delay.